


		32-Bit VME-SCSI Host Adapter

		Functional Specification


I. Mechanical

	A) The board will conform to the standard dual wide VME bus 
	specification of 160 mm X 233 mm.
	
	B) The 32-Bit VME-SCSI board will interface to the VME bus via two
	96-pin DIN connectors (P1 and P2).

	C) Interface to the SCSI bus will be accompolished via a 50-pin Non-
	shielded SCSI Device Connector as defined by ANSI X3.131-1986.


II. Environmental

	A) The 32-Bit VME-SCSI Host Adapter will operate under the following
	conditions:
		Temperature : 0 to 60 degrees Centigrade
		Humidity : 0 to 90 % noncondensing 
		Altitude : 0 to 10000 feet above sea level
	

III. Electrical
	
	A) The board will operate  form a single +5 VDC power supply. Power
	will be supplied to the board via the P1 and P2 VME connectors. The 
	board will be operational over a supply range of 4.75 to 5.25 VDC.


IV. Hardware

	The 32-Bit VME-SCSI Host Adapter will have the following features:

	A) The board will be designed around a Z8002 16-bit microprocessor.
	   The microprocessor will run at 8 MHz.
	B) EPROMs of the 2732A, 2732B, 2764, 27128 variety will be supported.
	   The EPROM used must have an access time of 200 nS minimum.
	C) The board will come standard with 64K bytes of high speed dual-ported
	   static RAM. For higher performance applications, the board will 
	   support 256K bytes of high speed dual-ported static RAM. The RAM is 
	   accessed via two DMA controllers. The first DMA controller handles 
	   8, 16, or 32 bit data transfers across the VME bus. 32 bit VME 
	   data transfers will achieved at a rate of 30+ MBytes per second. The
	   second DMA controller will handle data transfers between RAM and the
	   Fujitsu MB87030 SCSI Controller chip. 
	D) The SCSI interface will be controlled by a Fujitsu MB87030 controller	   chip. The Fujitsu chip is preferable to the NCR 5386S chip for 
	   architectural and performance reasons. The NCR device will NOT 
	   synchronous SCSI data transfers beyond 3.3 Mbytes per second. 
	   Fujitsu's controller has a seperate high speed data transfer bus 
	   over which DMA transfers occur. A second data transfer bus is
	   provided for communications to a microprocessor.
	E) Currently our GP-SCSI implementation requires the SCR register and
	   a semaphore register to be located in host memory. This requires
	   the VME-SCSI Host Adapter to become bus master and transfer the 
	   contents of these two registers to its internal buffer memory. This
	   will reduce the maximum achievable performance of the VME bus as
	   these data transfers are slow (~3 uS). The 32-Bit VME-SCSI Host
	   Adapter will have a dual-ported SCR register with a Semaphore lock
	   to accomodate host CPU read-modify-write cycles.
