
.\# $Header: sec2.t,v 1.2.1.2 86/04/03 16:08:57 chrisk Exp $
.nr H1 1
.aT "Cluster Node" "Cluster Node"
.ds aF Configuration
.DS
.TB "VME-68K20 Jumper Settings"
.TS
box, center;
c| c| c| c| c
l| l| l| l| lw(1.8i).
Jumpers	Default	Server	Cluster	Purpose
=
E1-E4	E1-2 to E6-1	E1-2 to E6-1	E1-2 to E1-1	T{
.fi
Sets the bus arbitration level to three (default zero) and disables the
on-board arbiter.
T}
E6	E1-3 to E6-2	E1-3 to E6-2	E2-1 to E2-2	\^
	E2-2 to E2-3	E2-2 to E2-3	E3-1 to E3-2	\^
	E3-2 to E3-3	E3-2 to E3-3	E4-2 to E6-1
	E4-2 to E4-3	E4-2 to E4-3	E4-1 to E6-2
_
E7-E10	E7-E12	E7-E12	E10-E12	T{
Sets the bus request level to three (default zero).
T}
E12				\^
_
E11	E11-1 to E11-2	E11-1 to E11-2	E11-1 to E11-2	T{
Defines this CPU as a Release When Done (RWD) bus master.
T}
_
E15-E20	E15 to E20-2	E15 to E20-2	E15 to E20-2	T{
Enables interprocessor in\%ter\%rupts.
T}
_
E16-E21	No jumpers	No jumpers	No jumpers	T{
Defines the interrupt level for vectored interprocessor in\%ter\%rupts.
Use setting #1 for the first cluster, and so on.
T}
E35-E37		E35-1 to E35-2	E35-1 to E35-2	   #1: E36-1 to E36-2	\^
		E36-1 to E36-2	E36-1 to E36-2	   E37-1 to E37-2	\^
		E37-1 to E37-2	E37-1 to E37-2 	#2: E37-1 to E37-2	\^
						   E35-1 to E35-2
						#3:E37-1 to E37-2
						#4: E35-1 to E35-2
						   E36-1 to E36-2
_
E17-E23	E17  E21	E17  E21	No jumpers	T{
Disables VME bus interrupts.
T}
	E18  E22	E18  E22
	E19  E23	E19  E23
	E20	E20
_
E24-E25	E24	E24	E24	T{
Sets console baud rate to 1200.
T}
_
E28-E31	E28	E28	#1: E31	T{
Assigns the cluster node ID.
Use setting #1 for the first cluster, and so on.
T}
	E29	E29	#2: E30	\^
	E30	E30	#3: E30, E31	\^
	E31	E31	#4: E29
_
E38-E39	No jumpers	No jumpers	E38	T{
Defines the base address for local memory (VME bus access to HSMEM).
T}
			E39	\^
_
E43 (A1)	E43-2 to E43-2	E43-2 to E43-3	E43-2 to E43-3	T{
Controls the boundary between VME bus access and HSMEM access in
non-translated virtual address space.
Use E45 for Etch A2 or later, E43 for Etch A1 of the board.
T}
 	 	 	 	\^
E45 (A2)	E45-2 to E45-3	E45-2 to E45-3	E45-2 to E45-3	\^
_
E43 (A1)	E43-2 to E43-3	E43-2 to E43-3	E43-2 to E43-3	T{
Uses 16-bit VME addressing.
Use E49 for Etch A2 or later, E45 for Etch A1 of the board.
T}
 	 	 	 	\^
E49 (A2)	E49-1 to E49-2	E49-1 to E49-2	E49-1 to E49-2	\^
_
S1				T{
Defines the amount of local memory accessible from the VME bus.
Bits as listed here should be closed (ON); all other bits should be
open (OFF).
T}
	S1-10	S1-10	S1-10	\^
.TE
.DE

****************************************************************

The folowing jumpers should be included in the above table:

1) E5-1 to E5-2		MC68881 Clock,

2)  E13 to E19-2	DARTINT*  Level 5,

3) E14 to E18-2		CTCINT*  Level 6,

4) E34-1 to E34-2	RAS Precharge,

5) E40-1 to E41 and	EPROM Size,
   E42-1 to E42-2

6) E44-1 to E44-3	On board I/O cycle length.

