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| XILINX APPLICATIONS NOTE XAPP023V-V1.00                   BN-5-16-94  |
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README file for the XC4000 32-bit accelerated counter:
======================================================

Note: A more detailed description of this application can be found in
Section 8 of the Xilinx Data Book.

Files included in XAPP023V.ZIP:
-------------------------------
  
  README          This readme file
  SCH\TEST32.1    Top-level test schematic
  SCH\HS32BIT.1   32-bit counter RPM
  SCH\MS_CNTR.*   MS 22 bits of the 32-bit counter
  SCN\LS_CNTR.1   LS 10 bits of the 32-bit counter
  SYM\            Schematic directory for the above macros   
  
  XNF\            XNF files
  TEST32.LCA      Routed design file
  TEST32.XRP      Xdelay timing report using XC4000-4

HS32BIT is an RPM that implements a slightly modified version of the 32-bit 
accelerated counter described in XAPP023. Unlike the data-book version, the 
counter is divided into 10- and 22-bit sections. A 10/22 split was chosen to 
balance the carry delay of the LS section and the CEP line with the carry 
delay of the MS section. In an XC4000-4, a settling time of 29.0 ns can be
achieved for a maximum clock frequency of 34.5 MHz.

Both count-enable (CE) and clock enable (EC) controls are provided. Parallel 
enable (PE) overrides the count enable, but not the clock enable.

A total of 20 CLBs are used, 7 for the LS counter and 13 for the MS counter. 
The two counter sections are implemented in separate columns, such that the 
counter can fit in an XC4005 or larger device.

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Performance:

Xdelay was used to report all clock-to-set-up paths. For the results, see the
XRP file.
