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| XILINX APPLICATIONS NOTE XAPP022V-V1.00                    BN-4-12-94 |
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README file for the XC3000A 8-bit Ultra-fast Counter:
=====================================================

Note: A more detailed description of this application can be found in
Section 8 of the Xilinx Data Book.

Files included in XAPP014V.ZIP:
-------------------------------
  
  README          This readme file
  SYM\UFASTCNT.1  8-bit ultra-fast-counter macro
  SCH\UFASTCNT.*  8-bit ultra-fast-counter macro
  SCH\3KCNT.1     Top-level schematic

  XNF\            XNF files
  3KCNT.LCA       Routed design file
  3KCNT.CST       Constraints File
  3KCNT.XR1       Xdelay timing report using XC3159A-3
  3KCNT.XR2       Xdelay timing report using XC3159A-3
  3KCNT.XR4       Xdelay timing report using XC3159A-3
  3KCNT.XR8       Xdelay timing report using XC3159A-3

This XAPP file provides a macro for an 8-bit ultr-fast counter, described in 
XAPP022. This macro is instantiated in a top-level design to illustrate the 
placement necessary to achieve the maximum performance. In XC3100A-3, the 
maximum clock frequency is 212 MHz.

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Implementation Notes:

  For maximum performance, all critical signals must be routed on direct
interconnect. To achieve this, the relative placement shown in the .LCA file 
should be used. One column of CLBs contains QO1, and $1-QXO1 through $1-QXO4 
in order below it. This permits the replicated LSBs to connect to each other 
using verticaldirect interconnect and to their associated counter bits using 
horizontal direct interconnect. The counter bits are placed in the column 
immediately to the right of the LSBs.  The carry logic is placed in the column
to the right of the counter bits. The constraints file is shown below.


# Placement Constraints for 3KCNT:
Place Block QO1 : AB;
Place Block QO2 : BC;
Place Block QO3 : CC;
Place Block QO5 : DC;
Place Block QO7 : EC;
Place Block $1-QXO1 : BB;
Place Block $1-QXO2 : CB;
Place Block $1-QXO3 : DB;
Place Block $1-QXO4 : EB;
Place Block $1-ANDQ3 : CD;
Place Block $1-ANDQ5 : DD;

Performance:

Some paths in this design have multiple clock periods in which to settle.
Xdelay was used to report the clock-to-set-up times for all paths within 
groups with the same settling time. The "From FF" filter was used to create 
four report files. The flip-flop groups and the results are shown below.

  1 Clock Period: $1-Q0B, $1-QX0*, $1-QY0*     4.7 ns   (3KCNT.XR1)
  2 Clock Periods: QO1, $1-CEP2                8.2 ns   (3KCNT.XR2)
  4 Clock Periods: QO2                         6.0 ns   (3KCNT.XR4)
  8 Clock Periods: All                        12.8 ns   (3KCNT.XR8)

As may be seen, the performance is limited by the 1-clock-period 
clock-to-set-up time of 4.7 ns (212 MHz).
