There are 13 ABEL files in this directory. Any of these may be compiled
into an XNF file for any of  Xilinx FPGA parts by running XABEL or ABL2XNF.
All ABEL designs for FPGAs referred to in the accompanying Xilinx ABEL User
Guide are included in this directory.

SCANNER1.ABL is a simple 4-state state machine.

SCANNER2.ABL shows how to use XILINX PROPERTY SAVE to retain specified
	     signals in the synthesised XNF file.

SCANNER3.ABL shows how to use XILINX PROPERTY MAP to control the mapping.

ELEVATOR.ABL contains a state machine for elevator control. It is 
	     referred to in the documentation to illustrate area-levels
	     trade-off during synthesis.

LA1.ABL      contains an example design with more than one interacting
	     state machines in it.

SEQUENCE.ABL is an example of a simple sequencer.

SMPLST3.ABL  is referred to in the documentation section on functional
	     simulation.

Z_ENCODE.ABL is an example of a user-encoded state machine.

ZIPCODE.ABL  is the symbolic state machine corresponding to Z_ENCODE.ABL

DSME1.ABL    contains a device-specific (P22V10) ABEL design.

DSME2.ABL    contains the device-independent version of DSME1.ABL

SBUSCNTL.ABL contains an SBUS Control circuit example.

STAT_ABL.ABL contains another symbolic state machine example used in
	     the tutorials shipped with other Xilinx software products.

Also included is a generic Jedec file fifo.jed to demonstrate the
program jed2hdlx which translates a JEDEC file into an ABEL-HDL file.

Also included is an example PALASM file counter.pds and the corresponding
ABEL-HDL file counter.abl to demonstrate the manual translation of
PALASM designs into ABEL.
