## $Header:instrs 12.0$ 
## $ACIS:instrs 12.0$ 
## $Source: /ibm/acis/usr/src/bin/as_ca/RCS/instrs,v $ 
##
##	Copyright (c) 1982 Regents of the University of California
##	@(#)instrs 4.9 6/30/83
##
##
##	THIS FILE IS BOTH AN AWK SCRIPT AND THE DATA.
##
##
##	This file is processed by an awk script, viz:
##	(echo "FLAVOR AS"; cat instrs) | awk -f instrs > as.instrs
##	(echo "FLAVOR ADB"; cat instrs) | awk -f instrs > as.instrs
##	(echo "FLAVOR SDB"; cat instrs) | awk -f instrs > as.instrs
##	(echo "FLAVOR C2"; cat instrs) | awk -f instrs > c2.instrs
##
##	The data in this file is shared among:
##	as	assembler
##	c2	optimizer
##	adb	debugger
##	sdb	symbolic debugger
##
##	The awk script reads itself and produces macros understood
##	by the appropriate consumer. The awk script determines how
##	to interpret the file by looking for a line of the form:
##	FLAVOR	AS
##	FLAVOR	ADB		(same as AS, but without pseudo instructions)
##	FLAVOR	SDB		(same as ADB)
##	FLAVOR	C2		(radically different format for instructions)
##	and proceeding accordingly.  This line should be prepended to
##	the front of this file.
##
##	Lines starting with ## are always comments to awk.
##	Lines starting with a single # are data lines to be output.
##	Empty lines are passed through.
##
##	Field	User(s)		Field name
##
##	$2	awk		#: comment to awk
##
##	$3	as, c2, adb	instruction name
##
##	$4	c2		instruction class
##
##	$5	c2		instruction subclass
##
##	$6	as, adb		escape opcode byte 
##
##	$7	as, adb		primary opcode byte
##	
##	$8	as, adb		number of arguments
##
##	$9	as, adb		1st operand: access type
##
##	$10	as, adb		1st operand: data type
##
##	$11	as, adb		2nd operand: access type
##	 .	  .		           .  	
##	 .	  .		           .	
##      $20	as, adb		6th operand: data type
##
##	N/A	as		last operand: instruction format
##
##
##	The explanations of these fields are as follows:
##
##	instruction class (c2):
##		This field is understood only by c2.  If it 
##		is HARD, the instruction subclass is ignored.
##		
##	instruction subclass (c2):
##		HARD		paired with the class
##		S		single valued attribute to C2
##		TN1		class + type of 1st operand
##		TN2		class + type of 2nd operand
##		TN3		class + type of 3rd operand
##		TNX2		class + type of 1st and 2nd operand
##		OP		class + type of 1st operand and # of args
##		default		class + subclass
##
##	escape byte:
##		CORE		8 bit op code, R and RI format instructions
##		ESCX		4 bit op code, X format instruction
##		ESDS		4 bit op code, D Short format instruction
##		ESJI		5 bit op code, JI format instruction
##		ESRD		8 bit op code, RD format instruction
##		ESBI		8 bit op code, BI and BIB format instructions
##		ESBA		8 bit op code, BA format instruction
##		ESCD		8 bit op code, D, DB, and D1 formats
##		ESCDUS		ditto, unsigned displacement
##		ESCDUP		ditto, upper half of reg
##		ESDI		8 bit op code, DI, DIN, and D2 formats
##		ESDIUS		ditto, unsigned immediate value
##	
##	access type:
##		AN		non-address referencing address
##		AR		readable address
##		AW		writable address
##		XR		label for branch or jump destination
##		GR		readable register
##		GW		writable register
##		GM		readable and writable register
##		IR		regular (signed) immediate data
##		IN		uNsigned immediate data
##
##	data length:
##		N		nibble
##		B		byte reference or bit number(0-7)
##              S       	short (2 bytes)
##		L		long (4 bytes)
##		U		double long (8 bytes)
##		F		floating point (32 bit)
##		D		floating point (64 bit)
##		Z		external reference permitted
##		Y		special cases
##
##	instruction format:
##		JI		5 bit op code, 2 byte instruction,
##				2 operands (operand 2 is a register)
##		ExtendedJI	5 bit op code, 2 byte instruction,
##				1 operand (a register)
##		X		4 bit op code, 2 byte instruction,
##				3 operands (all registers)
##		DShort		4 bit op code, 2 byte instruction,
##				2 operands (operand 1 is a register)
##		R		8 bit op code, 2 byte instruction,
##				2 operands (both registers)
##		RI		8 bit op code, 2 byte instruction,
##				2 operands (operand 1 is a register,
##				operand 2 is immediate data)
##		RD		8 bit op code, 2 byte instruction,
##				2 operands (operand 1 is a register,
##				operand 2 is a displacement)
##		RB		8 bit op code, 2 byte instruction,
##				2 operands (operand 2 is a register)
##		R0		8 bit op code, 2 byte instruction,
##				no operands
##		BI		8 bit op code, 4 byte instruction,
##				2 operands (operand 1 is a register,
##				operand 2 is a 20 bit displacement)
##		BIB		8 bit op code, 4 byte instruction,
##				2 operands (operand 2 is a 20 bit
##				displacement)
##		BA		8 bit op code, 4 byte instruction,
##				1 operand (a 24 bit absolute address)
##		D		8 bit op code, 4 byte instruction,
##				2 operands (operand 1 is a register,
##				operand 2 is a displacement)
##		DI		8 bit op code, 4 byte instruction,
##				3 operands (operands 1 and 2 are
##				registers, operand 3 is immediate data)
##		DIN		8 bit op code, 4 byte instruction,
##				3 operands (operand 2 is a register,
##				operand 3 is immediate data)
##		DB		8 bit op code, 4 byte instruction,
##				2 operands (operand 2 is a displacement)
##		D1		8 bit op code, 4 byte instruction,
##				1 operand (a displacement)
##		D2		8 bit op code, 4 byte instruction,
##				2 operands (operand 1 is a register,
##				operand 2 is immediate data)
##
##	The instructions are listed in the same order as in the
##	corresponding Principles of Operation.  However, the
##	order of instructions in this table is not critical.
##
##	The following is the awk program to interpret this table.

BEGIN{
	flavor = AS;
	##
	##	magic padding before the string for AS
	##	4 bytes of 0's: seek position of the string
	##	2 bytes, value 2, indicating core resident
	##	2 bytes, value 0, length
	##
	ASpad = "\\0\\0\\0\\0" "\\2\\0";
}
{
	if (NF == 0){
		printf("\n");
		next;
	}
	if ($1 == "FLAVOR"){
		flavor = $2;
		if (flavor == "SDB"){
			flavor = "ADB";
		}
		next;
	}
	if ($1 != "#"){
		next;
	}

	if ($6 == "MACR"){
		if (flavor == "ADB"){
			next;
		}
		if (flavor == "AS"){
			if ($4 == "CBR")
				$4 = "IJXXX";
			if ($4 == "SPEC")
				$4 = "ISPEC";
			printf("PSEUDO(\"%s\\0%o\\0%s\",", ASpad,length($3),$3);
			printf("%s, %s),\n", $7, $4);
			next;
		}
		if (flavor == "C2"){
			if ($5 == "C2X")
				next;
			printf("\"%s\",", $3);
			if ($4 == "CBR" && $5 != "JBR"){
				printf("T(CBR,%s),\n", $5);
			} else {
				printf("%s,\n", $5);
			}
			next;
		}
	}

	if (flavor == "C2"){
		printf("\"%s\",", $3);
		if ($4 == "HARD"){		# 0 value
			printf("0,\n");
			next;
		}
		if ($5 == "S"){			# single value
			printf("%s,\n", $4);
			next;
		}
		if ($5 == "TN1"){		# use type of 1st operand
			printf("T(%s,TYP%s),\n", $4, $10);
			next;
		}
		if ($5 == "TN3"){		# use type of 3rd operand
			printf("T(%s,TYP%s),\n", $4, $14);
			next;
		}
		if ($5 == "TNX2"){		# cross product of 1st and 2nd operand
			printf("T(%s,U(TYP%s,TYP%s)),\n", $4, $10, $12);
			next;
		}
		if ($5 == "OP"){		# arithmetic operator
			printf("T(%s,U(TYP%s,OP%d)),\n", $4, $10, $8);
			next;
		}
		printf("T(%s,%s),\n", $4, $5);	# special value
		next;
	}
	if (flavor == "AS"){
		printf("OP(\"%s\\0%o\\0%s\", ", ASpad, length($3), $3);
		printf("%s, %s, %d", $6, $7, $8);
	} else {
		printf("OP(\"%s\", %s, %s, %d", $3, $6, $7, $8);
	}
	if (flavor == "AS" || flavor == "ADB"){
		for (i = 9; i+1 <= NF; i = i + 2){
			printf(", A_%s%s", $i, $(i+1));
		}
		for (i = $8; i < 6; i++){
			printf(",0");
		}
		printf("),\n");
	}
}
##
##-------------------------------------------------------
##1 2  3	4	5	6    7		8  9  10
##
##
## PSEUDO (MACR) operators come first

## Data initializers

# 000a .byte	IBYTE	C2X	MACR 0		VAR
# 000b .short	ISHORT	WGEN	MACR 0		VAR
# 000c .int	IINT	LGEN	MACR 0		VAR
# 000d .long	ILONG	LGEN	MACR 0		VAR
# 000e .dlong	IDLONG	C2X	MACR 0		VAR
# 000a .float	IFFLOAT	C2X	MACR 0		VAR
# 000a .double	IDFLOAT	C2X	MACR 0		VAR
# 000a .hfloat  IHFLOAT C2X	MACR 0		VAR
# 000a .space	ISPACE	C2X	MACR 0		2
# 000a .fill	IFILL	C2X	MACR 0		3
# 000a .ascii	IASCII	C2X	MACR 0		VAR
# 000a .asciz	IASCIZ	C2X	MACR 0		VAR

# 000a .data	IDATA	DATA	MACR 0		1
# 000a .text	ITEXT	TEXT	MACR 0		1
# 000a .align	IALIGN	ALIGN	MACR 0		1
	
# 000a .line	ILINENO	C2X	MACR 0		1
# 000a .file	IFILE	C2X	MACR 0		1

# 000a .globl	IGLOBAL	EROU	MACR 0		1
# 000a .comm	ICOMM	COMM	MACR 0		2
# 000a .lcomm	ILCOMM	LCOMM	MACR 0		2
# 000a .set	ISET	SET	MACR 0		2
# 000a .lsym	ILSYM	C2X	MACR 0		2
# 000a .org	IORG	C2X	MACR 0		2
# 000a .using	IUSING	C2X	MACR 0		VAR
# 000a .ltorg	ILTORG	C2X	MACR 0		0

# 000a .stab	ISTAB	C2X	MACR 0		6
# 000a .stabd	ISTABDOT C2X	MACR 0		3
# 000a .stabn	ISTABNONE C2X	MACR 0		3
# 000a .stabs	ISTABSTR C2X	MACR 0		3

# 000a .ABORT	IABORT	C2X	MACR 0		0

## Registers

# 100a r0	REG	C2X	MACR 0		0
# 100a r1	REG	C2X	MACR 1		0
# 100a r2	REG	C2X	MACR 2		0
# 100a r3	REG	C2X	MACR 3		0
# 100a r4	REG	C2X	MACR 4		0
# 100a r5	REG	C2X	MACR 5		0
# 100a r6	REG	C2X	MACR 6		0
# 100a r7	REG	C2X	MACR 7		0
# 100a r8	REG	C2X	MACR 8		0
# 100a r9	REG	C2X	MACR 9		0
# 100a r10	REG	C2X	MACR 10		0
# 100a r11	REG	C2X	MACR 11		0
# 100a r12	REG	C2X	MACR 12		0
# 100a r13	REG	C2X	MACR 13		0
# 100a r14	REG	C2X	MACR 14		0
# 100a r15	REG	C2X	MACR 15		0
# 100a sp	REG	C2X	MACR 1		0
## 100a dp	REG	C2X	MACR 12		0
## 100a fp	REG	C2X	MACR 14		0

## Extended Branch Mnemonic Instructions

## Extended branch mnemonics for the bb instruction
# 200a nop	CBR	NOP	MACR 0x08	1  B B
# 200b btb	CBR	BTB	MACR 0x0f	1  B B
# 200c bc0	CBR	BC0	MACR 0x0c	1  B B
# 200d bl	CBR	BL	MACR 0x09	1  B B
# 200e bm	CBR	BM	MACR 0x09	1  B B
# 200f bh	CBR	BH	MACR 0x0b	1  B B
# 200g bp	CBR	BP	MACR 0x0b	1  B B
# 200h be	CBR	BE	MACR 0x0a	1  B B
# 200i beq	CBR	BEQ	MACR 0x0a	1  B B
# 200j bz	CBR	BZ	MACR 0x0a	1  B B
# 200k bo	CBR	BO	MACR 0x0e	1  B B
## Extended branch mnemonics for the bbx instruction
# 201a nopx	CBR	NOPX	MACR 0x18	1  B B
# 201b btbx	CBR	BTBX	MACR 0x1f	1  B B
# 201c bc0x	CBR	BC0X	MACR 0x1c	1  B B
# 201d blx	CBR	BLX	MACR 0x19	1  B B
# 201e bmx	CBR	BMX	MACR 0x19	1  B B
# 201f bhx	CBR	BHX	MACR 0x1b	1  B B
# 201g bpx	CBR	BPX	MACR 0x1b	1  B B
# 201h bex	CBR	BEX	MACR 0x1a	1  B B
# 201i beqx	CBR	BEQX	MACR 0x1a	1  B B
# 201j bzx	CBR	BZX	MACR 0x1a	1  B B
# 201k box	CBR	BOX	MACR 0x1e	1  B B
## Extended branch mnemonics for the bbr instruction
# 202a nopr	CBR	NOPR	MACR 0x28	1  B B
# 202b btbr	CBR	BTBR	MACR 0x2f	1  B B
# 202c bc0r	CBR	BC0R	MACR 0x2c	1  B B
# 202d blr	CBR	BLR	MACR 0x29	1  B B
# 202e bmr	CBR	BMR	MACR 0x29	1  B B
# 202f bhr	CBR	BHR	MACR 0x2b	1  B B
# 202g bpr	CBR	BPR	MACR 0x2b	1  B B
# 202h ber	CBR	BER	MACR 0x2a	1  B B
# 202i beqr	CBR	BEQR	MACR 0x2a	1  B B
# 202j bzr	CBR	BZR	MACR 0x2a	1  B B
# 202k bor	CBR	BOR	MACR 0x2e	1  B B
## Extended branch mnemonics for the bbrx instruction
# 203a noprx	CBR	NOPRX	MACR 0x38	1  B B
# 203b btbrx	CBR	BTBRX	MACR 0x3f	1  B B
# 203c bc0rx	CBR	BC0RX	MACR 0x3c	1  B B
# 203d blrx	CBR	BLRX	MACR 0x39	1  B B
# 203e bmrx	CBR	BMRX	MACR 0x39	1  B B
# 203f bhrx	CBR	BHRX	MACR 0x3b	1  B B
# 203g bprx	CBR	BPRX	MACR 0x3b	1  B B
# 203h berx	CBR	BERX	MACR 0x3a	1  B B
# 203i beqrx	CBR	BEQRX	MACR 0x3a	1  B B
# 203j bzrx	CBR	BZRX	MACR 0x3a	1  B B
# 203k borx	CBR	BORX	MACR 0x3e	1  B B
## Extended branch mnemonics for the bnb instruction
# 204a b	CBR	B	MACR 0x48	1  B B
# 204b bntb	CBR	BNTB	MACR 0x4f	1  B B
# 204c bnc0	CBR	BNC0	MACR 0x4c	1  B B
# 204d bnl	CBR	BNL	MACR 0x49	1  B B
# 204e bhe	CBR	BHE	MACR 0x49	1  B B
# 204f bnm	CBR	BNM	MACR 0x49	1  B B
# 204g bnh	CBR	BNH	MACR 0x4b	1  B B
# 204h ble	CBR	BLE	MACR 0x4b	1  B B
# 204i bnp	CBR	BNP	MACR 0x4b	1  B B
# 204j bne	CBR	BNE	MACR 0x4a	1  B B
# 204k bnz	CBR	BNZ	MACR 0x4a	1  B B
# 204l bno	CBR	BNO	MACR 0x4e	1  B B
## Extended branch mnemonics for the bnbx instruction
# 205a bx	CBR	BX	MACR 0x58	1  B B
# 205b bntbx	CBR	BNTBX	MACR 0x5f	1  B B
# 205c bnc0x	CBR	BNC0X	MACR 0x5c	1  B B
# 205d bnlx	CBR	BNLX	MACR 0x59	1  B B
# 205e bhex	CBR	BHEX	MACR 0x59	1  B B
# 205f bnmx	CBR	BNMX	MACR 0x59	1  B B
# 205g bnhx	CBR	BNHX	MACR 0x5b	1  B B
# 205h blex	CBR	BLEX	MACR 0x5b	1  B B
# 205i bnpx	CBR	BNPX	MACR 0x5b	1  B B
# 205j bnex	CBR	BNEX	MACR 0x5a	1  B B
# 205k bnzx	CBR	BNZX	MACR 0x5a	1  B B
# 205l bnox	CBR	BNOX	MACR 0x5e	1  B B
## Extended branch mnemonics for the bnbr instruction
# 206a br	CBR	BR	MACR 0x68	1  B B
# 206b bntbr	CBR	BNTBR	MACR 0x6f	1  B B
# 206c bnc0r	CBR	BNC0R	MACR 0x6c	1  B B
# 206d bnlr	CBR	BNLR	MACR 0x69	1  B B
# 206e bher	CBR	BHER	MACR 0x69	1  B B
# 206f bnmr	CBR	BNMR	MACR 0x69	1  B B
# 206g bnhr	CBR	BNHR	MACR 0x6b	1  B B
# 206h bler	CBR	BLER	MACR 0x6b	1  B B
# 206i bnpr	CBR	BNPR	MACR 0x6b	1  B B
# 206j bner	CBR	BNER	MACR 0x6a	1  B B
# 206k bnzr	CBR	BNZR	MACR 0x6a	1  B B
# 206l bnor	CBR	BNOR	MACR 0x6e	1  B B
## Extended branch mnemonics for the bnbrx instruction
# 207a brx	CBR	BRX	MACR 0x78	1  B B
# 207b bntbrx	CBR	BNTBRX	MACR 0x7f	1  B B
# 207c bnc0rx	CBR	BNC0RX	MACR 0x7c	1  B B
# 207d bnlrx	CBR	BNLRX	MACR 0x79	1  B B
# 207e bherx	CBR	BHERX	MACR 0x79	1  B B
# 207f bnmrx	CBR	BNMRX	MACR 0x79	1  B B
# 207g bnhrx	CBR	BNHRX	MACR 0x7b	1  B B
# 207h blerx	CBR	BLERX	MACR 0x7b	1  B B
# 207i bnprx	CBR	BNPRX	MACR 0x7b	1  B B
# 207j bnerx	CBR	BNERX	MACR 0x7a	1  B B
# 207k bnzrx	CBR	BNZRX	MACR 0x7a	1  B B
# 207l bnorx	CBR	BNORX	MACR 0x7e	1  B B

## Special Macro Instructions

## Special macro instructions for arithmetic instructions
# 210a sil	SPEC	SI	MACR 0x80	3  B B B
## Special macro instruction for move register
# 211a mr	SPEC	MR	MACR 0x81	2  B B
## Special macro instructions for add subtract and compare
# 212a add	SPEC	ADD	MACR 0x82	2  B B
# 212a ai	SPEC	ADD	MACR 0x82	3  B B B
# 213a sub	SPEC	SUB	MACR 0x83	2  B B
# 213a si	SPEC	SUB	MACR 0x83	3  B B B
# 214a cmp	SPEC	CMP	MACR 0x84	2  B B
# 214a ci	SPEC	CMP	MACR 0x84	2  B B
# 215a cmpl	SPEC	CMPL	MACR 0x85	2  B B
# 215a cli	SPEC	CMPL	MACR 0x85	2  B B
## Special macro instructions for logical operation instructions
# 220a ni	SPEC	NI	MACR 0x22	3  B B B
# 221a xi	SPEC	XI	MACR 0x21	3  B B B
# 222a oi	SPEC	OI	MACR 0x20	3  B B B
## Special macro instructions for shift instructions
# 230a shl	SPEC	SHL	MACR 0x40	2  B B
# 231a shla	SPEC	SHLA	MACR 0x41	2  B B
# 232a shr	SPEC	SHR	MACR 0x42	2  B B
# 233a shra	SPEC	SHRA	MACR 0x43	2  B B
## Special macro instructions for loading/storing registers
# 240a get	SPEC	GET	MACR 0x0f	2  B B
# 241a getha	SPEC	GETHA	MACR 0x0d	2  B B
# 242a geth	SPEC	GETH	MACR 0x08	2  B B
# 243a getc	SPEC	GETC	MACR 0x0c	2  B B
# 244a putc	SPEC	PUTC	MACR 0x09	2  B B
# 245a puth	SPEC	PUTH	MACR 0x0a	2  B B
# 246a put	SPEC	PUT	MACR 0x0b	2  B B
## ccom wishes this one
# 247a putha	SPEC	PUTH	MACR 0x0a	2  B B
## Special load/store macro instructions
# 250a load	SPEC	LOAD	MACR 0x10	2  B B
# 251a loadh	SPEC	LOADH	MACR 0x11	2  B B
# 252a loadha	SPEC	LOADHA	MACR 0x12	2  B B
# 253a loadc	SPEC	LOADC	MACR 0x13	2  B B
# 258a lda	SPEC    LDA	MACR 0x14	2  B B
# 254a store	SPEC	STORE	MACR 0x15	3  B B B
# 254a storeh	SPEC	STOREH	MACR 0x16	3  B B B
# 254a storeha	SPEC	STOREHA	MACR 0x17	3  B B B
# 254a storec	SPEC	STOREC	MACR 0x18	3  B B B

## Storage access instructions

# 300a lcs	HARD	HARD	ESDS 0x40	2  GW L  AR B		DShort
# 301a lc	HARD	HARD	ESCD 0xce	2  GW L  AR B		D
## 301b getc	HARD	HARD	ESCD 0xce	2  GW L  AR B		D
# 302a lhas	HARD	HARD	ESDS 0x50	2  GW L  AR S		DShort
# 303a lha	HARD	HARD	ESCD 0xca	2  GW L  AR S		D
## 303b getha	HARD	HARD	ESCD 0xca	2  GW L  AR S		D
# 304a lhs	HARD	HARD	ESRD 0xeb	2  GW L  AR S		RD
# 305a lh	HARD	HARD	ESCD 0xda	2  GW L  AR S		D
## 305b geth	HARD	HARD	ESCD 0xda	2  GW L  AR S		D
# 306a ls	HARD	HARD	ESDS 0x70	2  GW L  AR L		DShort
# 307a l	HARD	HARD	ESCD 0xcd	2  GW L  AR L		D
## 307b get	HARD	HARD	ESCD 0xcd	2  GW L  AR L		D
# 308a lm	HARD	HARD	ESCD 0xc9	2  GW L  AR L		D
# 309a tsh	HARD	HARD	ESCD 0xcf	2  GW L  AW S		D
# 310a stcs	HARD	HARD	ESDS 0x10	2  GR B  AW B		DShort
# 311a stc	HARD	HARD	ESCD 0xde	2  GR B  AW B		D
## 311b putc	HARD	HARD	ESCD 0xde	2  GR B  AW B		D
# 312a sths	HARD	HARD	ESDS 0x20	2  GR S  AW S		DShort
# 313a sth	HARD	HARD	ESCD 0xdc	2  GR S  AW S		D
## 313b putha	HARD	HARD	ESCD 0xdc	2  GR S  AW S		D
## 313c puth	HARD	HARD	ESCD 0xdc	2  GR S  AW S		D
# 314a sts	HARD	HARD	ESDS 0x30	2  GR L  AW L		DShort
# 315a st	HARD	HARD	ESCD 0xdd	2  GR L  AW L		D
## 315b put	HARD	HARD	ESCD 0xdd	2  GR L  AW L		D
# 316a stm	HARD	HARD	ESCD 0xd9	2  GR L  AW L		D

## Address computation instructions 

# 325a cal	HARD	HARD	ESCD 0xc8	2  GW L  AN L		D
# 326a cal16	HARD	HARD	ESCDUS 0xc2	2  GW L  AN L		D
# 327a cau	HARD	HARD	ESCDUP 0xd8	2  GW L  AN L		D
# 328a cas	HARD	HARD	ESCX 0x60	3  GW L  GR L  GR L	X
# 329a ca16	HARD	HARD	CORE 0xf3	2  GM L  GR L		R
# 330a inc	HARD	HARD	CORE 0x91	2  GM L  IN N		RI
# 331a dec	HARD	HARD	CORE 0x93	2  GM L  IN N		RI
# 332a lis	HARD	HARD	CORE 0xa4	2  GW L  IN N		RI

## Branching instructions

# 350a bala	HARD	HARD	ESBA 0x8a	1  XR L			BA
# 351a balax	HARD	HARD	ESBA 0x8b	1  XR L			BA
# 352a bali	HARD	HARD	ESBI 0x8c	2  GW L  XR L		BI
# 353a balix	HARD	HARD	ESBI 0x8d	2  GW L  XR L		BI
# 354a balr	HARD	HARD	CORE 0xec	2  GW L  GR L		R
# 355a balrx	HARD	HARD	CORE 0xed	2  GW L  GR L		R
# 356a jb	HARD	HARD	ESJI 0x11	2  IN B  XR L		JI
# 356b jnop	HARD	HARD	ESJI 0x08	1  XR L			ExtendedJI
# 356c jtb	HARD	HARD	ESJI 0x0f	1  XR L			ExtendedJI
# 356d jc0	HARD	HARD	ESJI 0x0c	1  XR L			ExtendedJI
# 356e jl	HARD	HARD	ESJI 0x09	1  XR L			ExtendedJI
# 356f jm	HARD	HARD	ESJI 0x09	1  XR L			ExtendedJI
# 356g jh	HARD	HARD	ESJI 0x0b	1  XR L			ExtendedJI
# 356h jp	HARD	HARD	ESJI 0x0b	1  XR L			ExtendedJI
# 356i je	HARD	HARD	ESJI 0x0a	1  XR L			ExtendedJI
# 356j jeq	HARD	HARD	ESJI 0x0a	1  XR L			ExtendedJI
# 356k jz	HARD	HARD	ESJI 0x0a	1  XR L			ExtendedJI
# 356l jo	HARD	HARD	ESJI 0x0e	1  XR L			ExtendedJI
# 357a bb	HARD	HARD	ESBI 0x8e	2  IN N  XR L		BIB
# 358a bbx	HARD	HARD	ESBI 0x8f	2  IN N  XR L		BIB
# 359a bbr	HARD	HARD	CORE 0xee	2  IN N  GR L		RB
# 360a bbrx	HARD	HARD	CORE 0xef	2  IN N  GR L		RB
# 361a jnb	HARD	HARD	ESJI 0x12	2  IN B  XR L		JI
# 361b j	HARD	HARD	ESJI 0x00	1  XR L			ExtendedJI
# 361c jntb	HARD	HARD	ESJI 0x07	1  XR L			ExtendedJI
# 361d jnc0	HARD	HARD	ESJI 0x04	1  XR L			ExtendedJI
# 361e jnl	HARD	HARD	ESJI 0x01	1  XR L			ExtendedJI
# 361f jhe	HARD	HARD	ESJI 0x01	1  XR L			ExtendedJI
# 361g jnm	HARD	HARD	ESJI 0x01	1  XR L			ExtendedJI
# 361h jnh	HARD	HARD	ESJI 0x03	1  XR L			ExtendedJI
# 361i jle	HARD	HARD	ESJI 0x03	1  XR L			ExtendedJI
# 361j jnp	HARD	HARD	ESJI 0x03	1  XR L			ExtendedJI
# 361k jne	HARD	HARD	ESJI 0x02	1  XR L			ExtendedJI
# 361l jnz	HARD	HARD	ESJI 0x02	1  XR L			ExtendedJI
# 361m jno	HARD	HARD	ESJI 0x06	1  XR L			ExtendedJI
# 362a bnb	HARD	HARD	ESBI 0x88	2  IN N  XR L		BIB
# 363a bnbx	HARD	HARD	ESBI 0x89	2  IN N  XR L		BIB
# 364a bnbr	HARD	HARD	CORE 0xe8	2  IN N  GR L		RB
# 365a bnbrx	HARD	HARD	CORE 0xe9	2  IN N  GR L		RB

## Trap instructions

# 375a ti	HARD	HARD	ESDI 0xcc	3  IN B  GR L  IR S	DIN
# 376a tgte	HARD	HARD	CORE 0xbd	2  GR L  GR L		R
# 377a tlt	HARD	HARD	CORE 0xbe	2  GR L  GR L		R

## Move and insert instructions

# 400a mc03	HARD	HARD	CORE 0xf9	2  GW B  GR B		R
# 401a mc13	HARD	HARD	CORE 0xfa	2  GW B  GR B		R
# 402a mc23	HARD	HARD	CORE 0xfb	2  GW B  GR B		R
# 403a mc33	HARD	HARD	CORE 0xfc	2  GW B  GR B		R
# 404a mc30	HARD	HARD	CORE 0xfd	2  GW B  GR B		R
# 405a mc31	HARD	HARD	CORE 0xfe	2  GW B  GR B		R
# 406a mc32	HARD	HARD	CORE 0xff	2  GW B  GR B		R
# 407a mftb	HARD	HARD	CORE 0xbc	2  GW N  GR N		R
# 408a mftbil	HARD	HARD	CORE 0x9d	2  GW N  IN N		RI
# 409a mftbiu	HARD	HARD	CORE 0x9c	2  GW N  IN N		RI
# 410a mttb	HARD	HARD	CORE 0xbf	2  GR N  GR N		R
# 411a mttbil	HARD	HARD	CORE 0x9f	2  GR N  IN N		RI
# 412a mttbiu	HARD	HARD	CORE 0x9e	2  GR N  IN N		RI

## Arithmetic instructions

# 425a a	HARD	HARD	CORE 0xe1	2  GM L  GR L		R
# 426a ae	HARD	HARD	CORE 0xf1	2  GM L  GR L		R
# 427a aei	HARD	HARD	ESDI 0xd1	3  GW L  GR L  IR S	DI
# 428a ail	HARD	HARD	ESDI 0xc1	3  GW L  GR L  IR S	DI
# 429a ais	HARD	HARD	CORE 0x90	2  GM L  IN N		RI
# 430a abs	HARD	HARD	CORE 0xe0	2  GW L  GR L		R
# 431a onec	HARD	HARD	CORE 0xf4	2  GW L  GR L		R
# 432a twoc	HARD	HARD	CORE 0xe4	2  GW L  GR L		R
# 433a c	HARD	HARD	CORE 0xb4	2  GR L  GR L		R
# 434a cis	HARD	HARD	CORE 0x94	2  GR L  IN N		RI
# 435a cil	HARD	HARD	ESDI 0xd4	2  GR L  IR S		D2
# 436a cl	HARD	HARD	CORE 0xb3	2  GR L  GR L		R
# 437a clil	HARD	HARD	ESDI 0xd3	2  GR L  IR S		D2
# 438a exts	HARD	HARD	CORE 0xb1	2  GW L  GR S		R
# 439a s	HARD	HARD	CORE 0xe2	2  GM L  GR L		R
# 440a sf	HARD	HARD	CORE 0xb2	2  GM L  GM L		R
# 441a se	HARD	HARD	CORE 0xf2	2  GM L  GR L		R
# 442a sfi	HARD	HARD	ESDI 0xd2	3  GW L  GR L  IR S	DI
# 443a sis	HARD	HARD	CORE 0x92	2  GM L  IN N		RI
# 444a d	HARD	HARD	CORE 0xb6	2  GM L  GR L		R
# 445a m	HARD	HARD	CORE 0xe6	2  GM L  GR L		R

## Logical operation instructions

# 450a clrbl	HARD	HARD	CORE 0x99	2  GM N  IN N		RI
# 451a clrbu	HARD	HARD	CORE 0x98	2  GM N  IN N		RI
# 452a setbl	HARD	HARD	CORE 0x9b	2  GM N  IN N		RI
# 453a setbu	HARD	HARD	CORE 0x9a	2  GM N  IN N		RI
# 454a n	HARD	HARD	CORE 0xe5	2  GM L  GR L		R
# 455a nilz	HARD	HARD	ESDIUS 0xc5	3  GW L  GR L  IN S	DI
# 456a nilo	HARD	HARD	ESDIUS 0xc6	3  GW L  GR L  IN S	DI
# 457a niuz	HARD	HARD	ESDIUS 0xd5	3  GW L  GR L  IN S	DI
# 458a niuo	HARD	HARD	ESDIUS 0xd6	3  GW L  GR L  IN S	DI
# 459a o	HARD	HARD	CORE 0xe3	2  GM L  GR L		R
# 460a oil	HARD	HARD	ESDIUS 0xc4	3  GW L  GR L  IN S	DI
# 461a oiu	HARD	HARD	ESDIUS 0xc3	3  GW L  GR L  IN S	DI
# 462a x	HARD	HARD	CORE 0xe7	2  GM L  GR L		R
# 463a xil	HARD	HARD	ESDIUS 0xc7	3  GW L  GR L  IN S	DI
# 464a xiu	HARD	HARD	ESDIUS 0xd7	3  GW L  GR L  IN S	DI
# 465a clz	HARD	HARD	CORE 0xf5	2  GW L  GR L		R

## Shift instructions

# 475a sar	HARD	HARD	CORE 0xb0	2  GM L  GR B		R
# 475b sra	HARD	HARD	CORE 0xb0	2  GM L  GR B		R
# 476a sari	HARD	HARD	CORE 0xa0	2  GM L  IN N		RI
# 477a sari16	HARD	HARD	CORE 0xa1	2  GM L  IN N		RI
# 478a sr	HARD	HARD	CORE 0xb8	2  GM L  GR B		R
# 479a sri	HARD	HARD	CORE 0xa8	2  GM L  IN N		RI
# 480a sri16	HARD	HARD	CORE 0xa9	2  GM L  IN N		RI
# 481a srp	HARD	HARD	CORE 0xb9	2  GM L  GR B		R
# 482a srpi	HARD	HARD	CORE 0xac	2  GM L  IN N		RI
# 483a srpi16	HARD	HARD	CORE 0xad	2  GM L  IN N		RI
# 484a sl	HARD	HARD	CORE 0xba	2  GM L  GR B		R
# 484b sla	HARD	HARD	CORE 0xba	2  GM L  GR B		R
# 485a sli	HARD	HARD	CORE 0xaa	2  GM L  IN N		RI
# 486a sli16	HARD	HARD	CORE 0xab	2  GM L  IN N		RI
# 487a slp	HARD	HARD	CORE 0xbb	2  GM L  GR B		R
# 488a slpi	HARD	HARD	CORE 0xae	2  GM L  IN N		RI
# 489a slpi16	HARD	HARD	CORE 0xaf	2  GM L  IN N		RI

## System control instructions

# 500a mts	HARD	HARD	CORE 0xb5	2  GW L  GR L		R
# 501a mfs	HARD	HARD	CORE 0x96	2  GR L  GW L		R
# 502a clrsb	HARD	HARD	CORE 0x95	2  GM N  IN N		RI
# 503a setsb	HARD	HARD	CORE 0x97	2  GM N  IN N		RI
# 504a lps	HARD	HARD	ESCD 0xd0	2  IN N  AR L		DB
# 505a wait	HARD	HARD	CORE 0xf0	0			R0
# 506a svc	HARD	HARD	ESCDUS 0xc0	1  AR S			D1

## Input/output instructions

# 525a ior	HARD	HARD	ESCDUS 0xcb	2  GW L  AR L		D
# 526a iow	HARD	HARD	ESCDUS 0xdb	2  GR L  AW L		D
